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Recent questions tagged co-and-architecture

3 votes
1 answer
2224
DMA CONTROLLER CYCLE STEALING
Please explain DMA cycle stealing mode with a timeline diagram. Does the DMA wait for 1 byte before aquiring the bus control and is this the same time when CPU utilizes the bus for it's own purpose ?
Please explain DMA cycle stealing mode with a timeline diagram.Does the DMA wait for 1 byte before aquiring the bus control and is this the same time when CPU utilizes th...
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0 votes
1 answer
2227
UGC NET CSE | June 2011 | Part 2 | Question: 34
In which way(s) a macroprocessor for assembly language can be implemented? Independent two-pass processor Independent one-pass processor Expand macrocalls and substitute arguments All of the above
In which way(s) a macroprocessor for assembly language can be implemented?Independent two-pass processorIndependent one-pass processorExpand macrocalls and substitute arg...
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2 votes
1 answer
2230
General doubt
For incrementing or decrementing the value of Program Counter (PC), is switching to Kernel mode required?
For incrementing or decrementing the value of Program Counter (PC), is switching to Kernel mode required?
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3 votes
1 answer
2233
What does n-word block size mean? Following example from Computer Organization by Petterson, Hennessey.
"Assuming a cache of 4K blocks, a 4-word block size, and a 32‐bit address, find the total number of sets and the total number of tag bits for caches that are direct map...
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2 votes
2 answers
2236
UGC NET CSE | December 2011 | Part 2 | Question: 31
CPU does not perform the operation Data transfer Logic operation Arithmetic operation All of the above
CPU does not perform the operationData transferLogic operationArithmetic operationAll of the above
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4 votes
3 answers
2238
UGC NET CSE | June 2016 | Part 2 | Question: 48
Pipelining improves performance by decreasing instruction latency eliminating data hazards exploiting instruction level parallelism decreasing the cache miss rate
Pipelining improves performance bydecreasing instruction latencyeliminating data hazardsexploiting instruction level parallelismdecreasing the cache miss rate
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11 votes
3 answers
2240
Cycle Stealing(DMA)
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
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3 votes
4 answers
2243
UGC NET CSE | December 2015 | Part 3 | Question: 2
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
What will be the output at $\text{PORT1 }$if the following program is executed?MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT$37H$$82H$$B9H$$00H$
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0 votes
0 answers
2244
Cache memory access time
If the question is given, L1 cache access time is 150ns/word and one block of L1 cache contains 5words. Should I multiply the access time by 5 or leave it at 150ns as memory is word addressable?
If the question is given, L1 cache access time is 150ns/word and one block of L1 cache contains 5words.Should I multiply the access time by 5 or leave it at 150ns as memo...
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1 votes
1 answer
2245
A processor has a 16 bit data bus and 32 bit address bus, what is the maximum byte locations it can address
A processor has a 16 bit data bus and 32 bit address bus, what is the maximum byte locations it can address
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1 votes
1 answer
2246
Microprocessor UGCNET
A computer with $32$ bit wide data bus user $4k \times 8$ static RAM memory chips. The smallest memory this computer can have is...? $32$kb $16$kb $8$KB $24$kb
A computer with $32$ bit wide data bus user $4k \times 8$ static RAM memory chips. The smallest memory this computer can have is...?$32$kb$16$kb$8$KB$24$kb
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